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general description the max13171e along with the max13173e/ MAX13175E, form a complete pin-selectable data termi- nal equipment (dte) or data communication equipment (dce) interface port that support the v.28 (rs-232), v.10/v.11 (rs-449/v.36, rs-530, rs-530a, x.21), and v.35 protocols. the max13171e transceivers carry the high-speed clock and data signals, while the max13173e transceivers carry the control signals. the max13171e can be terminated by the MAX13175E pin-selectable resistor termination network. the MAX13175E contains six pin-selectable, multiprotocol cable termination networks. the max13171e/max13173e have an internal charge pump and low-dropout transmitter output stages that allow v.10-, v.11-, v.28-, and v.35-compliant operation from a single supply. the max13171e/max13173e fea- ture a no-cable mode that reduces supply current and disables all transmitter and receiver outputs (high imped- ance). short-circuit current limiting and thermal shutdown circuitry protects the receiver and transmitter outputs against excessive power dissipation. the max13171e/ max13173e have extended esd protection for all the transmitter outputs and receivers inputs. the max13171e/max13173e/MAX13175E operate over the +3.135v to +5.5v supply range and are available in 5mm x 7mm, 38-pin tqfn packages. these devices oper- ate over the -40? to +85? extended temperature range. applications features ? supports v.28 (rs-232), v.10 (rs-423), v.11 (rs-449/v.36, rs-530, rs-530a, x.21) and v.35 protocols ? pin-selectable cable termination using the MAX13175E ? pin-selectable dce/dte configurations ? 20/40mbps (max) data rate in rs-449, rs-530, rs-530a, x.21, and v.35 ? true fail-safe receivers while maintaining v.11 and v.35 compatibility ? operates over a wide +3.135v to +5.5v v cc supply range ? flexible v l logic reference input allows interfacing down to 1.62v ? extended esd protection for all the transmitter outputs and receivers inputs to gnd ? small, 5mm x 7mm, 38-pin tqfn package max13171e/max13173e/MAX13175E multiprotocol, pin-selectable data interface chipset ________________________________________________________________ maxim integrated products 1 ordering information t1 t2 t3 t4 r1 r2 r3 max13171e rxd rxc txd txc scte t1 t2 t3 r1 r2 r3 max13173e cts dsr rts dtr dcd rxc b rxd a (104) rxd b sg (102) shield (101) rts a (105) rts b dtr a (108) dtr b dcd a (107) dcd b dsr a (109) cts a (106) dsr b cts b ll a (141) txd b scte a (113) scte b txc a (114) txc b txd a (103) db-25 connector 13 r4 ll rxc a (115) 18 5 10 8 22 6 23 20 19 4 1 7 16 3 9 17 12 15 11 24 14 2 MAX13175E typical operating circuit 19-4595; rev 1; 7/09 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. part temp range pin- package max13171e etu+ - 40c to + 85c 38 tqfn-ep* max13173e etu+ - 40c to + 85c 38 tqfn-ep* MAX13175E etu+ - 40c to + 85c 38 tqfn-ep* data networking pci cards csu and dsu telecommunication equipment data routers data switches
max13171e/max13173e/MAX13175E multiprotocol, pin-selectable data interface chipset 2 _______________________________________________________________________________________ absolute maximum ratings max13171e electrical characteristics (v cc = +3.135v to +5.5v, v l = +1.62v to +5.5v, c1 = c2 = 1?, c3 = c4 = c5 = 4.7? (figure 15), t a = -40? to +85?, unless oth- erwise noted. typical values are at v cc = +3.3v, v l = +1.8v, t a = +25?.) (note 2) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to http://www.maxim-ic.com/thermal-tutorial . (all voltages to gnd, unless otherwise noted.) supply voltages v cc ........................................................................ -0.3v to +6v v l ........................................................................... -0.3v to +6v v ee ..................................................................... +0.3v to -7.1v v dd .................................................................... -0.3v to +7.1v v dd to v cc ............................................................-0.3v to +6v logic-input voltages m0, m1, m2, dce/ dte , latch , invert, t_in ..... -0.3v to +6v termination network inputs r_a, r_b, r_c.......................................................-15v to +15v r_a to r_b (only for high-z state) .....................................?4v r_a to r_b...........................................................................?v r_a to r_c (only for high-z state) .....................................?4v r_a to r_c...........................................................................?v r_b to r_c (only for high-z state) .......................................?v logic-output voltages r_out ........................................................-0.3v to (v l + 0.3v) transmitter outputs t_out_, t_out_/r_in_ (no-cable, v.28, v.10 modes) ...............................-15v to +15v short-circuit duration to gnd..................................continuous receiver inputs r_in_, t_out_/r_in ............................................-15v to +15v r_ina to r_inb, t3outa/r3ina to t3outb/r3inb ................................................-15v to +15v continuous power dissipation (t a = +70?) 38-pin tqfn (derate 35.7mw/? above +70?) ........2857mw junction-to-case thermal resistance ( jc ) (note 1) 38-pin tqfn ....................................................................1?/w junction-to-ambient thermal resistance ( ja ) (note 1) 38-pin tqfn ..................................................................28?/w operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range ............................-65? to +150? lead temperature (soldering, 10s) ................................+300? parameter symbol conditions min typ max units v cc operating range v cc 3.135 5.5 v v l operating range v l 1.62 v cc v v l supply current i l all inputs connected to gnd, all receiver outputs low, v l = +5.5v 550 800 ? rs-530, rs-530a, x.21, v.36/rs-449 mode (v.11), no load 15 28 ma rs-530, rs-530a, x.21, v.36/rs-449 mode (v.11), full load 150 200 ma v.35 mode, no load 21 38 ma v.35 mode, full load 150 210 ma v.28 mode, no load 15 30 ma v.28 mode, full load 28 42 ma v cc supply current (dce mode) (digital inputs = gnd or v cc ) (transmitter outputs static) i cc no-cable mode 0.01 10 ? rs-530, rs-530a, x.21, v.36/rs-449 mode (v.11), full load 100 v.35 mode, full load 500 internal power dissipation (dce mode)(static) p d v.28 mode, full load 70 mw
max13171e/max13173e/MAX13175E multiprotocol, pin-selectable data interface chipset _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units v.28, v.35 modes, no load (note 3) 5.93 7.1 v.28 mode, full load (note 3) 5.6 5.86 v.35 mode, full load (note 3) 4.6 5.1 rs - 530, rs - 530a, x .21, v .36/rs - 449 m od e ( v .11) ( n ote 3) 4.9 5.26 5.7 positive charge-pump output voltage v dd no-cable mode v cc v v.28, v.35 modes, no load (note 3) -5.89 v.28 mode, full load (note 3) -5.74 -5.4 v.35 mode, full load, note 3 -4.46 -3.8 rs - 530, rs - 530a, x .21, v .36/rs - 449 m od e ( v .11) ( n ote 3) -4.84 -4.47 -4.16 negative charge-pump output voltage v ee no-cable mode 0 v charge-pump enable time time until all v dd and v ee specifications meet < 1 ms thermal shutdown protection thsd +145 ? logic inputs (m0, m1, m2, dce/ dte , t1in, t2in, t3in) input high voltage v ih 0.66 x v l v input low voltage v il 0.33 x v l v logic-input current i in t1in, t2in, t3in -1 +1 ? pullup resistor r puin m0, m1, m2, dce/ dte to v l 50 100 170 k ? logic outputs (r1out, r2out, r3out) output high voltage v oh i source = 4ma 0.66 x v l v output low voltage v ol i sink = 4ma 0.33 x v l v output pullup resistor r puy no-cable mode (to v l ) 71.4 k ? v.11 transmitter open-circuit differential output voltage v odo open circuit, r = 1.95k ? , figure 1 -v cc +v cc v r = 50 ? , figure 1 0.5 x v odo loaded differential output voltage v odl r = 50 ? , figure 1 i2i v change in magnitude of output differential voltage | ? v od | r = 50 ? , figure 1 0.2 v common-mode output voltage v oc r = 50 ? , figure 1 3.0 v change in magnitude of common-mode output voltage | ? v oc | r = 50 ? , figure 1 (note 3) 0.2 v short-circuit current i sc v out = gnd 150 ma rise time t r figures 2, 6 4.5 ns fall time t f figures 2, 6 6.5 ns max13171e electrical characteristics (continued) (v cc = +3.135v to +5.5v, v l = +1.62v to +5.5v, c1 = c2 = 1?, c3 = c4 = c5 = 4.7? (figure 15), t a = -40? to +85?, unless oth- erwise noted. typical values are at v cc = +3.3v, v l = +1.8v, t a = +25?.) (note 2)
max13171e/max13173e/MAX13175E multiprotocol, pin-selectable data interface chipset 4 _______________________________________________________________________________________ max13171e electrical characteristics (continued) (v cc = +3.135v to +5.5v, v l = +1.62v to +5.5v, c1 = c2 = 1?, c3 = c4 = c5 = 4.7? (figure 15), t a = -40? to +85?, unless oth- erwise noted. typical values are at v cc = +3.3v, v l = +1.8v, t a = +25?.) (note 2) parameter symbol conditions min typ max units figures 2, 6 22 28 transmitter input to output propagation delay (figures 2, 6) t phl , t plh v l +3v, figures 2, 6 20 25 ns data skew |t phl -t plh | figures 2, 6 (note 3) 2 ns channel-to-channel skew t skew figures 2, 6 (notes 3, 4) 3 ns v.11 receiver differential threshold voltage v th -7v v cm +7v -200 -50 mv input hysteresis ? v th -7v v cm +7v 15 mv receiver input current i in -10v v a,b +10v -0.66 +0.66 ma receiver input resistance r in -10v v a,b +10v 15 30 k ? rise or fall time t r , t f figures 2, 7 3 ns receiver input to output delay t phl , t plh figures 2, 7 2.5 ns data skew |t phl -t plh | figures 2, 7 (note 3) 3 ns channel-to-channel skew t skewr figures 2, 7 (notes 3, 4) 3 ns v.35 transmitter differential output voltage v od full load, -4v < v cm < +4v, figure 3 ?.44 ?.55 ?.66 v output high current i oh v a,b = 0v -13 -11 -9 ma output low current i ol v a,b = 0v 9 11 13 ma output leakage current i z -0.25v v out +0.25v, power off or no-cable mode ?.05 ? ? rise or fall time t r , t f figures 3, 6 5 ns transmitter input to output delay t plh , t phl figures 3, 6 19 35 ns data skew |t plh - t phl | figures 3, 6 (note 3) 3 ns channel-to-channel skew t skewr figures 3, 6 (notes 3, 4) 3 ns v.35 receiver differential threshold voltage v th -2v v cm +2v -200 -50 mv input hysteresis ? v th -2v v cm +2v 15 mv receiver input current i in -10v v a,b +10v -0.66 +0.66 ma receiver input resistance r in -10v v a,b +10v 15 30 k ? rise or fall time t r , t f figures 3, 7 3 ns receiver input to output delay t phl , t plh figures 3, 7 25 ns data skew |t phl - t plh | figures 3, 7 (note 3) 3 ns channel-to-channel skew t skewr figures 3, 7 (notes 3, 4) 3 ns v.28 transmitter open circuit 7.1 output-voltage swing |v od | r l = 3k ? 56 v short-circuit current i oh 85 ma
max13171e/max13173e/MAX13175E multiprotocol, pin-selectable data interface chipset _______________________________________________________________________________________ 5 max13171e electrical characteristics (continued) (v cc = +3.135v to +5.5v, v l = +1.62v to +5.5v, c1 = c2 = 1?, c3 = c4 = c5 = 4.7? (figure 15), t a = -40? to +85?, unless oth- erwise noted. typical values are at v cc = +3.3v, v l = +1.8v, t a = +25?.) (note 2) parameter symbol conditions min typ max units output leakage current i z -0.25v v out +0.25v, power off or no-cable mode ?.05 ? ? output slew rate sr r/f r l = 3k ? , c l = 2500pf (swing in ?v), figures 4, 10 4 30 v/? transmitter input to output delay t phl , t plh r l = 3k ? , c l = 2500pf, figures 4, 10 1 2 ? v.28 receiver input threshold low v il 0.8 1.2 v input threshold high v ih 1.2 2 v input hysteresis v hyst 0.25 v input resistance r in -15v v in +15v 3 5 7 k ? rise or fall time t r , t f figures 5, 11 3 ns receiver input to output delay t phl , t plh figures 5, 11 150 ns esd protection human body model ?5 air gap discharge iec 61000-4-2 ?2 t_out, t3out_/r1in_, r_in to gnd contact discharge iec 61000-4-2 ? kv max13173e electrical characteristics (v cc = +3.135v to +5.5v, v l = +1.62v to +5.5v, c1 = c2 = 1?, c3 = c4 = c5 = 4.7? (figure 15), t a = -40? to +85?, unless otherwise noted. typical values are at v cc = +3.3v, v l = +1.8v, t a = +25?.) (note 2) parameter symbol conditions min typ max units v cc operating range v cc 3.135 5.5 v v l operating range v l 1.62 v cc v v l supply current i l all inputs connected to gnd, all receiver outputs low, v l = +5.5v 680 1100 ? rs-530a, no load 11 21 ma rs-530, x.21, v.36/rs-449, dce mode, invert = low, full load, transmitter outputs static, digital inputs = gnd or v l 41 210 ma v.28 mode, no load 21 38 ma v.28 mode, full load 42 65 ma v cc supply current i cc no-cable mode 0.01 10 ? internal power dissipation p d rs-530, x.21, v.36/rs-449; dce mode, invert = low, full load 120 mw v.28 mode, no load (note 3) 5.9 7.1 v.28 mode with full load (note 3) 5.6 5.79 rs-530 mode, full load (note 3) 4.84 5.15 5.5 rs-530a mode, full load 5.15 positive charge-pump output voltage v dd no-cable mode v cc v
max13171e/max13173e/MAX13175E multiprotocol, pin-selectable data interface chipset 6 _______________________________________________________________________________________ max13173e electrical characteristics (continued) (v cc = +3.135v to +5.5v, v l = +1.62v to +5.5v, c1 = c2 = 1?, c3 = c4 = c5 = 4.7? (figure 15), t a = -40? to +85?, unless otherwise noted. typical values are at v cc = +3.3v, v l = +1.8v, t a = +25?.) (note 2) parameter symbol conditions min typ max units v.28 mode, no load (note 3) -5.83 v.28 mode with full load (note 3) -5.55 -5.3 rs-530 mode, full load (note 3) -4.71 -4.44 -4.17 rs-530a mode, full load -4.44 negative charge-pump output voltage v ee no-cable mode 0 v thermal shutdown protection thsd +145 ? charge-pump enable time time until all v dd and v ee specifications meet < 1 ms logic inputs (m0, m1, m2, dce/ dte , invert, t1in, t2in, t3in, t4in, t5in/r5out) input high voltage v ih 0.66 x v l v input low voltage v il 0.33 x v l v logic-input current i in t1in, t2in, t3in, t4in -1 +1 a pullup resistor r puin m0, m1, m2, dce/ dte , invert to v l 50 100 170 k ? logic outputs (r1out, r2out, r3out, r4out, t5in/r5out) output high voltage v oh i source = 4ma 0.66 x v l v output low voltage v ol i sink = 4ma 0.33 x v l v output pullup resistor r puy no-cable mode (to v l ) 71.4 k ? v.11 transmitter (t1, t2, t3) open-circuit differential output voltage v odo open circuit, r = 1.95k ? , figure 1 -v cc +v cc v r = 50 ? , figure 1 0.5 x v odo loaded differential output voltage v odl r = 50 ? , figure 1 |2| v change in magnitude of output differential voltage | ? v od | r = 50 ? , figure 1 0.2 v common-mode output voltage v oc r = 50 ? , figure 1 3.0 v change in magnitude of common-mode output voltage | ? v oc | r = 50 ? , figure 1 (note 3) 0.2 v short-circuit current i sc v out = gnd 150 ma output leakage current i z -0.25v v out +0.25v, power-off or no- cable mode ?.05 ? ? rise time t r figures 2, 6 4 10 ns fall time t f figures 2, 6 6 10 ns figures 2, 6 20 28 ns transmitter input to output prop delay t phl , t plh figures 2, 6, v l +3v 25 ns data skew |t phl - t plh | figures 2, 6 (note 3) 2 ns channel-to-channel skew t skew figures 2, 6 (notes 3, 4) 3 ns
max13171e/max13173e/MAX13175E multiprotocol, pin-selectable data interface chipset _______________________________________________________________________________________ 7 max13173e electrical characteristics (continued) (v cc = +3.135v to +5.5v, v l = +1.62v to +5.5v, c1 = c2 = 1?, c3 = c4 = c5 = 4.7? (figure 15), t a = -40? to +85?, unless otherwise noted. typical values are at v cc = +3.3v, v l = +1.8v, t a = +25?.) (note 2) parameter symbol conditions min typ max units v.11 receiver (r1, r2, r3) differential threshold voltage v th -7v v cm +7v -200 -50 mv input hysteresis ? v th -7v v cm +7v 15 mv receiver input current i in -10v v a,b +10v -0.66 +0.66 ma receiver input resistance r in -10v v a,b +10v 15 30 k ? rise or fall time t r , t f figures 2, 7 3 ns receiver input to output delay t phl , t plh figures 2, 7 27 ns data skew |t phl - t plh | figures 2, 7 (note 3) 3 ns channel-to-channel skew t skewr figures 2, 7 (notes 3, 4) 3 ns v.10 transmitter (t2, t4, t5) r l = 3.9k ? (out high) 4 6 open-circuit output voltage swing v o r l = 3.9k ? (out low) -6 -4 v r l = 450 ? (out high) 3.6 r l = 450 ? (out low) -3.6 output-voltage swing v t r l = 450 ? 0.9 x |v o | v short-circuit current i sc v o = gnd -55 +55 ma output leakage current i z -0.25v v out +0.25v, power-off or no-cable mode ?.05 +5 ? rise or fall time t r , t f r l = 450 ? , c l = 100pf, figure 8 2 ? transmitter input to output delay t plh , t phl r l = 450 ? , c l = 100pf, figure 8 1 ? v.10 receiver (r2, r4, r5) input threshold voltage v th 50 250 mv input hysteresis ? v th 25 mv receiver input current i in -10v v a +10v -0.66 +0.66 ma receiver input resistance r in -10v v a +10v 15 30 k ? rise or fall time t r , t f figures 5, 9 3 ns t plh figure 9 55 receiver input to output delay t phl figure 9 109 ns data skew |t phl - t plh | figures 5, 9 (note 3) 60 ns v.28 transmitter (all channels) open circuit 7.1 output-voltage swing |v od | r l = 3k ? 56 v short-circuit current i oh 90 ma output leakage current i z -0.25v v out +0.25v, power-off or no-cable mode ?.05 ? ?
max13171e/max13173e/MAX13175E multiprotocol, pin-selectable data interface chipset 8 _______________________________________________________________________________________ max13173e electrical characteristics (continued) (v cc = +3.135v to +5.5v, v l = +1.62v to +5.5v, c1 = c2 = 1?, c3 = c4 = c5 = 4.7?, figure 15, t a = -40? to +85?, unless otherwise noted. typical values are at v cc = +3.3v, v l = +1.8v, t a = +25?.) (note 2) parameter symbol conditions min typ max units output slew rate sr r/f r l = 3k ? , c l = 2500pf (swing in ?v) figures 4, 10 4 30 v/? transmitter input to output delay t phl , t plh r l = 3k ? , c l = 2500pf, figures 4, 10 1 2 ? v.28 receiver (all channels) input threshold low v il 0.8 1.2 v input threshold high v ih 1.2 2 v input hysteresis v hyst 0.25 v input resistance r in -15v v in +15v 3 5 7 k ? rise or fall time t r , t f figures 5, 11 3 ns receiver input to output delay t phl , t plh figures 5, 11 150 ns esd protection human body model ?5 air gap discharge iec 61000-4-2 ?5 t_out, t_out/r_in_, r_in contact discharge ? kv MAX13175E electrical characteristics (continued) (v cc = +3.135v to +5.5v, v l = +1.62v to +5.5v, c1 = c2 = 1?, c3 = c4 = c5 = 4.7?, figure 15, t a = -40? to +85?, unless otherwise noted. typical values are at v cc = +3.3v, v l = +1.8v, t a = +25?.) (note 2) parameter symbol conditions min typ max units v cc operating range v cc 3.135 5.5 v v l operating range v l 1.62 v cc v v dd operating range v dd 4.5 7.1 v v ee operating range v ee -7.1 -4 v v l por rising threshold 0.7 1.06 1.46 v v cc por rising threshold 1 1.88 2.75 v v dd supply current i dd all inputs connected to gnd or v l , except no-cable mode 0.05 0.25 ma i cc all inputs connected to gnd or v l , except no-cable mode 2.15 5.9 ma v cc supply current i cc_nocab v ee = 0v, m[x] = 1111 (note 5) 1.29 2.6 ma v l supply current i l all inputs connected to gnd or v l -1 +1 ? v ee supply current i ee all inputs connected to gnd or v l -3.5 -1 ma terminator inputs differential-mode impedance v.35 mode -2v v cm +2v, all channels, figure 12 90 104 110 ? common-mode impedance v.35 mode -2v v cm +2v, all channels, figure 13 135 153 165 ?
max13171e/max13173e/MAX13175E multiprotocol, pin-selectable data interface chipset _______________________________________________________________________________________ 9 note 2: all devices are 100% production tested at t a = +85? for the max13171e/max13173e and t a = +25? for the MAX13175E. specifications over temperature are guaranteed by design. note 3: guaranteed by design, not production tested. note 4: output-to-output skews are evaluated as difference of propagation delays between different channels in the same condition and for the same polarity (lh or hl). note 5: m[x] is the input bus dte/ dce , m2, m1, m0. MAX13175E electrical characteristics (continued) (v cc = +3.135v to +5.5v, v l = +1.62v to +5.5v, c1 = c2 = 1?, c3 = c4 = c5 = 4.7?, figure 15, t a = -40? to +85?, unless otherwise noted. typical values are at v cc = +3.3v, v l = +1.8v, t a = +25?.) (note 2) parameter symbol conditions min typ max units -7v v cm +7v, all channels, except no- cable mode, figure 12 100 104 110 differential-mode impedance v.11 mode -7v v cm +7v, no cable, v ee = 0v, v ab < 2v, figure 12 115 ? differential path enable time 50 ? differential path disable time 300 ? common-mode path enable time 12 ? common-mode path disable time 2s high-impedance leakage current i z -15v v r_a +15v -50 +50 ? logic inputs (m0, m1, m2, latch , dce/ dte ) input high voltage v ih 0.66 x v l v input low voltage v il 0.33 x v l v logic input current i in v in = gnd or v l -1 +1 ? esd protection human body model ?5 air gap discharge iec 61000-4-2 ?0 r_a, r_b to gnd contact discharge iec 61000-4-2 ? kv all other pins human body model ? kv
max13171e/max13173e/MAX13175E multiprotocol, pin-selectable data interface chipset 10 ______________________________________________________________________________________ v.35 loaded differential output voltage vs. common-mode voltage max13171e toc07 common-mode voltage (v) differential output voltage (mv) -2 0 2 535 540 545 555 550 560 530 -4 4 dc output |v od | v.11/v.35 receiver input current vs. input voltage max13171e toc08 input voltage (v) input current ( a) 8 0 -2 2 -8 -400 -300 0 200 100 -200 -100 400 300 500 -500 -10 10 4 -4 -6 6 dc output dte mode r2ina, r3ina r1ina v.28 receiver input current vs. input voltage max13171e toc09 input voltage (v) input current (ma) 8 0 -2 2 -8 -2.0 -1.5 0 1.0 0.5 -1.0 -0.5 2.0 1.5 2.5 -2.5 -10 10 4 -4 -6 6 dc output dte mode v.11 differential output voltage vs. temperature max13171e toc04 temperature ( c) differential output voltage (v) 60 35 10 -15 -2 -1 0 1 2 3 -3 -40 85 v out+ v out- dc output dce mode, r = 50 ? v.28 output voltage vs. temperature max13171e toc05 temperature ( c) output voltage (v) 60 35 -15 10 -6 -4 -2 0 4 2 6 8 -8 -40 85 dc output dce mode, r l = 3k ? v out+ v out- v.35 output voltage vs. temperature max13171e toc06 temperature ( c) output voltage (v) 60 35 -15 10 -400 -200 0 400 200 600 -600 -40 85 dc output dce mode, v cm = 0v, full load v oh v ol max13171e typical operating characteristics (v cc = +3.3v, v l = +1.8v, t a = +25?, unless otherwise noted.) rs-530 supply current vs. data rate max13171e toc01 data rate (kbps) supply current (ma) 1000 10 50 100 150 200 250 300 350 0 0.1 10,000 dce mode, r = 50 ? , all transmitters operating at the specified data rate v.28 supply current vs. data rate max13171e toc02 data rate (kbps) supply current (ma) 200 150 50 100 10 20 30 40 60 50 70 80 0 0250 dce mode, all transmitters operating at the specified data rate, r l = 3k ? , c l = 2500pf v.35 supply current vs. data rate max13171e toc03 data rate (kbps) supply current (ma) 1000 10 50 100 150 200 250 300 350 0 0.1 10,000 dce mode, fully loaded, all transmitters operating at the specified data rate
max13171e/max13173e/MAX13175E multiprotocol, pin-selectable data interface chipset ______________________________________________________________________________________ 11 v.11/v.35 receiver propagation delay vs. temperature max13171e toc14 temperature ( c) propagation delay (ns) 10 35 10 14 12 8 4 6 2 18 16 20 0 -40 85 60 -15 t phl t plh v.11 transmitter propagation delay vs. temperature max13171e toc15 temperature ( c) propagation delay (ns) 10 35 15 10 5 20 25 0 -40 85 60 -15 t phl t plh v.35 transmitter propagation delay vs. temperature max13171e toc16 temperature ( c) propagation delay (ns) 10 35 15 25 10 5 20 30 0 -40 85 60 -15 t phl t plh v.35 loopback operation (40mbps) max13171e toc12 1 v.28 slew rate vs. load capacitance max13171e toc13 load capacitance (pf) slew rate (v/ s) 2000 3000 10 20 15 5 30 25 35 0 05000 4000 1000 r l = 3k ? sr f sr r max13171e typical operating characteristics (continued) (v cc = +3.3v, v l = +1.8v, t a = +25?, unless otherwise noted.) v.11 loopback operation (40mbps) max13171e toc10 10ns/div r_out 2v/div t_out_/r_in_ 2v/div t_in 2v/div r = 50 ? v.28 loopback operation (250kbps) max13171e toc11 1 s/div r_out 2v/div t_out_/r_in_ 5v/div t_in 2v/div r l = 3k ? , c l = 2500pf
max13171e/max13173e/MAX13175E multiprotocol, pin-selectable data interface chipset 12 ______________________________________________________________________________________ max13173e typical operating characteristics (v cc = +3.3v, v l = +1.8v, t a = +25?, unless otherwise noted.) v.28 supply current vs. data rate max13171e toc18 data rate (kbps) supply current (ma) 200 100 150 50 10 20 30 40 50 60 70 80 90 0 0250 dce mode, invert = 1 all transmitters operating at the specified data rate full load, r l = 50 ? , c l = 2500pf no load v.11 differential output voltage vs. temperature max13171e toc19 temperature ( c) differential output voltage (v) 60 35 -15 10 -3 -2 -1 0 2 1 3 4 -4 -40 85 dc output dce mode, invert = 1, r = 50 ? v out+ v out- v.10 output voltage vs. temperature max13171e toc20 temperature ( c) output voltage (v) 60 35 -15 10 -6 -4 -2 0 4 2 6 8 -8 -40 85 dc output dce mode v out+ r l = 3.9k ? r l = 3.9k ? r l = 450 ? v out- v.28 output voltage vs. temperature max13171e toc21 temperature ( c) output voltage (v) 60 35 -15 10 -6 -4 -2 0 4 2 6 8 -8 -40 85 dc output dce mode, r l = 3k ? v out+ v out- v.11 receiver input current vs. input voltage max13171e toc22 input voltage (v) input current ( v) 6 2 -6 -2 -400 -300 -200 0 200 100 300 -100 400 500 -500 -10 10 4 0 -8 -4 8 dc output dce mode r3ina r2ina r1ina v.28 receiver input current vs. input voltage max13171e toc23 input voltage (v) input current (ma) -5 5 -3 -2 -1 0 2 1 3 4 -4 -15 15 010 -10 dc output r-530 supply current vs. data rate max13171e toc17 data rate (kbps) supply current (ma) 10 1000 50 100 150 200 250 0 0 100,000 dce mode, invert = 1 3 transmitters operating at the specified data rate in v.11 mode full load, r = 50 ? no load, r = 1.95k ?
max13171e/max13173e/MAX13175E multiprotocol, pin-selectable data interface chipset ______________________________________________________________________________________ 13 v.11 transmitter propagation delay vs. temperature max13171e toc30 temperature ( c) propagation delay (ns) 60 35 -15 10 10 5 20 15 25 0 -40 85 t phl t plh v.28 slew rate vs. load capacitance max13171e toc24 load capacitance (pf) slew rate (v/ s) 2000 3000 10 20 15 5 30 25 35 0 0 5000 4000 1000 r l = 3k ? sr f sr r v.10 transmitter rise/fall time vs. load capacitance max13171e toc25 load capacitance (pf) rise/fall time ( s) 2000 3000 1.0 1.4 1.2 0.8 0.4 0.6 0.2 1.8 1.6 2.0 0 0 5000 4000 1000 fall rise v.11 loopback operation (40mbps) max13171e toc26 10ns/div r_out 2v/div t_out_/r_in_ 2v/div t_in 2v/div full load v.28 loopback operation (250kbps) max13171e toc27 1 ? , c l = 2500pf v.10 loopback operation (100kbps) max13171e toc28 4 ? r l = 450 ? v.11 receiver propagation delay vs. temperature max13171e toc29 temperature ( c) propagation delay (ns) 60 35 -15 10 10 5 20 15 25 0 -40 85 t phl t plh max13173e typical operating characteristics (continued) (v cc = +3.3v, v l = +1.8v, t a = +25?, unless otherwise noted.)
max13171e/max13173e/MAX13175E multiprotocol, pin-selectable data interface chipset 14 ______________________________________________________________________________________ v.11 or v.35 differential impedance vs. temperature MAX13175E toc31 temperature ( n c) impedance ( i ) 60 35 10 -15 101 102 103 104 105 106 107 108 109 110 100 -40 85 v cm = -7v v cm = +7v v cm = 0v v.11 or v.35 differential impedance vs. common-mode voltage (v cm ) v cm (v) impedance ( i ) MAX13175E toc32 101 102 103 104 105 106 107 108 109 110 100 5 3 -1 1 -3 -5 -7 7 v.11 or v.35 differential impedance vs. supply voltage (v cc ) MAX13175E toc33 v cc (v) impedance ( i ) 5.0 4.5 4.0 3.5 101 102 103 104 105 106 107 108 109 110 100 3.0 5.5 v.11 or v.35 differential impedance vs. supply voltage (v ee ) v ee (v) -5 -6 -7 -4 MAX13175E toc34 impedance ( i ) 101 102 103 104 105 106 107 108 109 110 100 v.35 common-mode impedance vs. temperature 60 35 10 -15 140 145 150 155 160 165 135 -40 85 MAX13175E toc35 temperature ( n c) impedance ( i ) v cm = +2v v cm = -2v v . 35 common-mode impedance vs . common-mode voltage (v cm ) v cm (v) 1 0 -1 140 145 150 155 160 165 170 175 180 185 135 -2 2 MAX13175E toc36 impedance ( i ) MAX13175E typical operating characteristics (v cc = +3.3v, v l = +1.8v, t a = +25?, unless otherwise noted.)
max13171e/max13173e/MAX13175E v.11 or v.35 differential impedance phase vs. frequency frequency (mhz) phase (degrees) 10 1 -30 -25 -20 -15 -10 -5 0 5 10 15 -35 0.1 100 m ax13175e t oc41 multiprotocol, pin-selectable data interface chipset ______________________________________________________________________________________ 15 v.35 common-mode impedance vs. supply voltage 5.0 4.5 4.0 3.5 140 145 150 155 160 165 135 3.0 5.5 MAX13175E toc37 v cc (v) impedance ( i ) v cm = +2v v cm = -2v v.35 common-mode impedance vs. supply voltage (v ee ) v ee (v) -5 -6 -7 -4 MAX13175E toc38 140 145 150 155 160 165 135 impedance ( i ) v cm = +2v v cm = -2v hi-z mode supply current vs. temperature supply current ( f a) 60 35 -15 10 100 200 300 400 600 500 700 800 0 -40 85 MAX13175E toc39 temperature ( n c) i cc i ee v.11 or v.35 differential impedance magnitude vs. frequency frequency (mhz) 10 1 20 40 60 80 100 120 0 0.1 100 m ax13175e t oc40 i m pedance ( i ) MAX13175E typical operating characteristics (continued) (v cc = +3.3v, v l = +1.8v, t a = +25?, unless otherwise noted.)
max13171e/max13173e/MAX13175E multiprotocol, pin-selectable data interface chipset 16 ______________________________________________________________________________________ max13171e pin description pin name function 1, 2, 6, 30, 31 n.c. no connection. not internally connected. 3, 16 v cc device supply voltage. bypass v cc with a 4.7? capacitor to ground as close as possible to pin 3. 4 t1in transmitter 1 logic input 5 t2in transmitter 2 logic input 7 t3in transmitter 3 logic input 8 r1out receiver 1 logic output with internal pullup to v l 9 r2out receiver 2 logic output with internal pullup to v l 10 r3out receiver 3 logic output with internal pullup to v l 11 m0 mode-select 0 input with internal pullup to v l 12 v l logic-supply reference input. v l determines the voltage level of the logic interface. bypass v l with a 0.1? capacitor to ground as close as possible to the device. 13 m1 mode-select 1 input with internal pullup to v l 14 m2 mode-select 2 input with internal pullup to v l 15 dce/ dte dce/ dte mode-select input with internal pullup to v l 17 r3inb receiver 3 noninverting input 18 r3ina receiver 3 inverting input 19, 24, 29, 35 gnd ground 20 r2inb receiver 2 noninverting input 21 r2ina receiver 2 inverting input 22 t3outb/r1inb transmitter 3 noninverting output/receiver 1 noninverting input 23 t3outa/r1ina transmitter 3 inverting output/receiver 1 inverting input 25 t2outb transmitter 2 noninverting output 26 t2outa transmitter 2 inverting output 27 t1outb transmitter 1 noninverting output 28 t1outa transmitter 1 inverting output 32 v ee charge-pump negative supply output. connect a 4.7? ceramic capacitor from v ee to ground as close as possible to the device. 33 c2- v ee charge-pump flying-capacitor negative terminal. connect a 1? ceramic capacitor between c2+ and c2-. 34 c2+ v ee charge-pump flying-capacitor positive terminal. connect a 1? ceramic capacitor between c2+ and c2-. 36 c1- v dd charge-pump flying-capacitor negative terminal. connect a 1? ceramic capacitor between c1+ and c1-. 37 c1+ v dd charge-pump flying-capacitor positive terminal. connect a 1? ceramic capacitor between c1+ and c1-. 38 v dd charge-pump positive-supply output. connect a 4.7? ceramic capacitor from v dd to ground as close as possible to the device. ?p exposed pad. internally connected to v ee . connect to a large v ee plane to maximize thermal performance. not intended as an electrical connection point. do not share the same plane as the max13173e.
max13171e/max13173e/MAX13175E multiprotocol, pin-selectable data interface chipset ______________________________________________________________________________________ 17 max13173e pin description pin name function 1 t1in transmitter 1 logic input 2v cc device supply voltage. bypass v cc with a 4.7? capacitor to ground as close as possible to the device. 3 t2in transmitter 2 logic input 4 t3in transmitter 3 logic input 5v l logic-supply reference input. v l determines the voltage level of the logic interface. bypass v l with a 0.1? capacitor to ground, as close as possible to the device. 6 r1out receiver 1 logic output with internal pullup to v l 7 r2out receiver 2 logic output with internal pullup to v l 8 r3out receiver 3 logic output with internal pullup to v l 9 r5out/t5in receiver 5 logic output/transmitter 5 logic input 10 t4in transmitter 4 logic input 11 r4out receiver 4 logic output 12 m0 mode-select 0 input with internal pullup to v l 13 m1 mode-select 1 input with internal pullup to v l 14 m2 mode-select 2 input with internal pullup to v l 15 dce/ dte dce/ dte mode-select input with internal pullup to v l 16 invert t4/r4 and t5/r5 s el ect inp ut w i th inter nal p ul l up to v l . in v e rt r ever ses the acti on of dce/ dte for channels 4 and 5. 17 t4outa/r4ina transmitter 4 inverting output/receiver 4 inverting input 18, 25, 31, 35 gnd ground 19 r3inb receiver 3 noninverting input 20 r3ina receiver 3 inverting input 21 r2inb receiver 2 noninverting input 22 r2ina receiver 2 inverting input 23 t3outb/r1inb transmitter 3 noninverting output/receiver 1 noninverting input 24 t3outa/r1ina transmitter 3 inverting output/receiver 1 inverting input 26 t2outb transmitter 2 noninverting output 27 t2outa transmitter 2 inverting output 28 t1outb transmitter 1 noninverting output 29 t1outa transmitter 1 inverting output 30 t5outa/r5ina transmitter 5 inverting output/receiver 5 inverting input 32 v ee charge-pump negative-supply output. connect a 4.7? ceramic capacitor from v ee to ground as close as possible to the device. 33 c2- v ee charge-pump flying-capacitor negative terminal. connect a 1? ceramic capacitor between c2+ and c2-. 34 c2+ v ee charge-pump flying-capacitor positive terminal. connect a 1? ceramic capacitor between c2+ and c2-. 36 c1- v dd charge-pump flying-capacitor negative terminal. connect a 1? ceramic capacitor between c1+ and c1-.
max13171e/max13173e/MAX13175E multiprotocol, pin-selectable data interface chipset 18 ______________________________________________________________________________________ max13173e pin description (continued) pin name function 37 c1+ v dd charge-pump flying-capacitor positive terminal. connect a 1? ceramic capacitor between c1+ and c1-. 38 v dd charge-pump positive-supply output. connect a 4.7? ceramic capacitor from v dd to ground as close as possible to the device. ?p exposed pad. internally connected to v ee . connect to a large v ee plane to maximize thermal performance, not intended as an electrical connection point. does not share the same plane as the max13171e. MAX13175E pin description pin name function 1, 38 r1b load 1, node b 2, 3 r1a load 1, node a 4, 5 r2a load 2, node a 6, 7 r2b lode 2, node b 8 r2c lode 2, center tap 9, 10 r3a load 3, node a 11, 12 r3b lode 3, node b 13, 18 gnd ground 14 r3c lode 3, center tap 15 v l logic-supply reference input. v l determines the voltage level of the logic interface. 16 v ee negative supply voltage. bypass v ee to gnd with a 0.1? capacitor. connect to v ee from the max13173e. 17 v dd positive supply voltage. bypass v dd to gnd with a 0.1? capacitor. connect to v dd from the max13173e. 19 v cc supply voltage. bypass v cc to gnd with a 0.1? capacitor as close as possible to the device. 20, 21 r4b load 4, node b 22, 23 r4a load 4, node a 24, 25 r5b load 5, node b 26, 27 r5a load 5, node a 28, 29 r6a load 6, node a 30, 31 r6b load 6, node b 32 dce/ dte dce/ dte mode-select input 33 latch latch signal input. when latch is low, the input latches are transparent. when latch is high, the data at the mode-select inputs are latched. 34 m2 mode-select input 2 35 m1 mode-select input 1 36 m0 mode-select input 0 37 r1c load 1, center tap ?p exposed pad. internally connected to v ee . connect to a large v ee plane to maximize thermal performance, not intended as an electrical connection point. if v ee is powered from the max13173e? v ee , planes can be shared.
max13171e/max13173e/MAX13175E multiprotocol, pin-selectable data interface chipset ______________________________________________________________________________________ 19 test circuits v oc r a b r v od figure 1. v.11 dc test circuit v cm 15pf 50 ? 50 ? 125 ? 125 ? 50 ? 50 ? r b a b a t v od figure 3. v.35 transmitter/receiver test circuit figure 2. v.11 ac test circuit 100pf 15pf 100pf 100 ? r b a b a t c l r l v o a t figure 4. v.10/v.28 transmitter test circuit figure 5. v.10/v.28 receiver test circuit t a r 15pf
max13171e/max13173e/MAX13175E multiprotocol, pin-selectable data interface chipset 20 ______________________________________________________________________________________ timing diagrams v l /2 90% 10% 50% t plh v l 0v v 0 -v 0 tin_ b - a t r v l /2 t phl 90% 10% 50% t f f = 1mhz: t r , t f 1ns figure 6. v.11 transmitter propagation delays +1v -1v v 0h v 0l b - a r 0 input output 0 t plh t phl f = 1mhz: t r , t f 1ns v l /2 v l /2 90% 10% t r 90% 10% t f figure 7. v.11 receiver propagation delays 0 t phl 0v v 0h -v 0l tin_ a 10% 90% t f 0 t plh 90% 10% t r t r , t f 10ns v l /2 v l /2 v l figure 8. v.10 transmitter propagation delay v ih v il v 0h v 0l a r 0 t phl 0 t plh t r , t f 10ns v l /2 v l /2 90% 10% t f 90% 10% t r figure 9. v.10 receiver propagation delay
max13171e/max13173e/MAX13175E multiprotocol, pin-selectable data interface chipset ______________________________________________________________________________________ 21 timing diagrams (continued) 0 t phl 0v v 0h -v 0l tin_ a -3v 3v t f sr f = 6/t f sr r = 6/t r 0 t plh 3v -3v t r t r , t f 10ns v l /2 v l /2 v l figure 10. v.28 transmitter propagation delay v ih v il (2.0v) (0.8v) v 0h v 0l a r 1.3v t phl 1.3v t plh t r , t f 10ns v l /2 v l /2 90% 10% t f 90% 10% t r figure 11. v.28 receiver propagation delay v cm = 7v or 2v v dm = 2v r dm = v dm r2 = 52 ? r3 = 127 ? r1 = 52 ? s1 on a i i b s2 off ammeter figure 12. v.11 or v.35 differential impedance measurement v cm = 2v r2 = 52 ? r3 = 127 ? r1 = 52 ? s1 on a b s2 on ammeter r cm = v cm i i figure 13. v.35 common-mode impedance measurement
max13171e/max13173e/MAX13175E multiprotocol, pin-selectable data interface chipset 22 ______________________________________________________________________________________ r1a r2a r2b r3a r3b r4a r4b r5a r5b r6a r6b m2 m1 m0 r1b dce/dte latch MAX13175E v l v cc v dd v ee gnd v ee ep r1c r2c r3c figure 14. MAX13175E block diagram detailed description the max13171e/max13173e/MAX13175E form a com- plete pin-selectable dte or dce interface port that supports the v.28 (rs-232), v.10/v.11 (rs-449/v.36, rs-530, rs-530a, x.21), and v.35 protocols. the max13171e transceivers carry the high-speed clock and data signals, while the max13173e transceivers carry serial-interface control signaling. the max13171e can be terminated by the MAX13175E pin-selectable resistor termination network, or by a discrete termina- tion network. the max13171e/max13173e feature a low supply current, no-cable mode, true fail-safe opera- tion, and thermal-shutdown circuitry. thermal shutdown protects the drivers against excessive power dissipa- tion. when activated, the thermal-shutdown circuitry places the driver and receiver outputs into a high- impedance state. the max13171e is a three-driver/three-receiver, multi- protocol transceiver that operates from a single +3.135v to +5.5v supply. the max13173e is a five-dri- ver/five-receiver multiprotocol transceiver that operates from a single +3.135v to +5.5v supply. the MAX13175E contains six pin-selectable multiprotocol cable termination networks (figure 14). each network is capable of terminating v.11 (rs-422, rs-530, rs-530a, rs-449, v.36 and x.21) with a 100 ? differential load, v.35 with a t-network load, or v.28 (rs-232) and v.10 (rs-423) with an open-circuit load for use with trans- ceivers having on-chip termination. the terminations and protocols are pin selectable. the MAX13175E replaces discrete resistor termination networks and expensive relays required for multiprotocol termination, saving space and cost. dual charge-pump voltage converter the max13171e/max13173e have internal-regulated dual charge pumps that provide positive and negative output voltages from a single supply. the charge pump operates in discontinuous mode. if the output voltage is less than the regulated voltage, the charge pump is enabled. if the output voltage exceeds the regulated voltage, the charge pump is disabled. each charge pump requires flying capacitors (c1, c2), and reservoir capacitors (c3, c5), to generate the v dd and v ee sup- plies. figure 15 shows the charge-pump connections. c2- v ee c2+ max13171e max13173e gnd c1- +3.135v to +5.5v v cc v dd c1+ c1 1 f c5 4.7 f c2 1 f c3 4.7 f c4 4.7 f figure 15. charge pump
max13171e/max13173e/MAX13175E multiprotocol, pin-selectable data interface chipset ______________________________________________________________________________________ 23 fail-safe the max13171e/max13173e guarantee a logic-high receiver output when the receiver inputs are shorted, or when they are connected to a terminated transmission line with all drivers disabled by setting the receiver threshold between -50mv and -200mv in the v.11 and v.35 modes. if the differential receiver input voltage (b - a) is -50mv, r_out is logic-high. if (b - a) is -200mv, r_out is logic-low. in the case of a terminated bus with all transmitters disabled, the receiver? differential input voltage is pulled to zero by the termination. this results in a logic-high with a 50mv minimum noise margin. the v.10 receiver threshold is set between 50mv and 250mv. if the v.10 receiver input voltage is less than or equal to 50mv, r_out is logic-high. the v.28 receiver threshold is set between 0.8v and 2.0v. if the receiver input voltage is less than or equal to 0.8v, r_out is logic-high. in the case of a terminated bus with trans- mitters disabled, the receiver? input voltage is pulled to gnd by the termination. mode selection the mode-select inputs m0, m1, and m2 determine which interface protocol is selected (table 1 for the max13171e, table 2 for the max13173e). the state of the dce/ dte input determines whether the transceivers are configured as a dte serial port or a dce serial port. the invert input on the max13173e changes the dce/ dte functionality regarding t4/t5 and r4/r5 only. m0, m1, m2, invert, and dce/ dte are internally pulled up to v l to ensure logic-high if left unconnected. if the m0, m1, and m2 mode inputs are all unconnect- ed, the max13171e/max13173e enter no-cable mode. the MAX13175E mode select inputs and dce/ dte input do not have an internal pullup to v l . they are pulled logic-high if their mode-select inputs are tied to the max13171e/max13173e? mode select inputs. termination modes the termination networks in the MAX13175E can be set to one of three modes, v.11, v.35, or high impedance. max13171e mode name m2 m1 m0 dce/ dte t1 t2 t3 r1 r2 r3 not used (default v.11) 0 0 0 0 v.11 v.11 z v.11 v.11 v.11 rs-530a 0 0 1 0 v.11 v.11 z v.11 v.11 v.11 rs-530 0 1 0 0 v.11 v.11 z v.11 v.11 v.11 x.21 0 1 1 0 v.11 v.11 z v.11 v.11 v.11 v.35 1 0 0 0 v.35 v.35 z v.35 v.35 v.35 rs-449/v.36 1 0 1 0 v.11 v.11 z v.11 v.11 v.11 v.28/rs-232 1 1 0 0 v.28 v.28 z v.28 v.28 v.28 no cable 1 1 1 0 z z z z z z not used (default v.11) 0 0 0 1 v.11 v.11 v.11 z v.11 v.11 rs-530a 0 0 1 1 v.11 v.11 v.11 z v.11 v.11 rs-530 0 1 0 1 v.11 v.11 v.11 z v.11 v.11 x.21 0 1 1 1 v.11 v.11 v.11 z v.11 v.11 v.35 1 0 0 1 v.35 v.35 v.35 z v.35 v.35 rs-449/v.36 1 0 1 1 v.11 v.11 v.11 z v.11 v.11 v.28/rs-232 1 1 0 1 v.28 v.28 v.28 z v.28 v.28 no cable 1 1 1 1 z z z z z z table 1. max13171e mode selection
max13171e/max13173e/MAX13175E multiprotocol, pin-selectable data interface chipset 24 ______________________________________________________________________________________ protocol m2 m1 m0 dce/ dte inver tt1 t2 t3 r1r2r3t4r4t5r5 not used (default v.11) 0 0 0 0 0 v.11 v.11 z v.11 v.11 v.11 z v.10 z v.10 rs-530a 0 0 1 0 0 v.11 v.10 z v.11 v.10 v.11 z v.10 z v.10 rs-530 0 1 0 0 0 v.11 v.11 z v.11 v.11 v.11 z v.10 z v.10 x.21 0 1 1 0 0 v.11 v.11 z v.11 v.11 v.11 z v.10 z v.10 v.35 1 0 0 0 0 v.28 v.28 z v.28 v.28 v.28 z v.28 z v.28 rs-449/v.36 1 0 1 0 0 v.11 v.11 z v.11 v.11 v.11 z v.10 z v.10 v.28/rs-232 1 1 0 0 0 v.28 v.28 z v.28 v.28 v.28 z v.28 z v.28 no cable 1 1 1 0 0 z z z z z z z z zz not used (default v.11) 0 0 0 0 1 v.11 v.11 z v.11 v.11 v.11 v.10 z v.10 z rs-530a 0 0 1 0 1 v.11 v.10 z v.11 v.10 v.11 v.10 z v.10 z rs-530 0 1 0 0 1 v.11 v.11 z v.11 v.11 v.11 v.10 z v.10 z x.21 0 1 1 0 1 v.11 v.11 z v.11 v.11 v.11 v.10 z v.10 z v.35 1 0 0 0 1 v.28 v.28 z v.28 v.28 v.28 v.28 z v.28 z rs-449/v.36 1 0 1 0 1 v.11 v.11 z v.11 v.11 v.11 v.10 z v.10 z v.28/rs-232 1 1 0 0 1 v.28 v.28 z v.28 v.28 v.28 v.28 z v.28 z no cable 1 1 1 0 1 z z z z z z z z z z not used (default v.11) 0 0 0 1 0 v.11 v.11 v.11 z v.11 v.11 v.10 z v.10 z rs-530a 0 0 1 1 0 v.11 v.10 v.11 z v.10 v.11 v.10 z v.10 z rs-530 0 1 0 1 0 v.11 v.11 v.11 z v.11 v.11 v.10 z v.10 z x.21 0 1 1 1 0 v.11 v.11 v.11 z v.11 v.11 v.10 z v.10 z v.35 1 0 0 1 0 v.28 v.28 v.28 z v.28 v.28 v.28 z v.28 z rs-449/v.36 1 0 1 1 0 v.11 v.11 v.11 z v.11 v.11 v.10 z v.10 z v.28/rs-232 1 1 0 1 0 v.28 v.28 v.28 z v.28 v.28 v.28 z v.28 z no cable 1 1 1 1 0 z z z z z z z z z v.10 not used (default v.11) 0 0 0 1 1 v.11 v.11 v.11 z v.11 v.11 z v.10 z v.10 rs-530a 0 0 1 1 1 v.11 v.10 v.11 z v.10 v.11 z v.10 z v.10 rs-530 0 1 0 1 1 v.11 v.11 v.11 z v.11 v.11 z v.10 z v.10 x.21 0 1 1 1 1 v.11 v.11 v.11 z v.11 v.11 z v.10 z v.10 v.35 1 0 0 1 1 v.28 v.28 v.28 z v.28 v.28 z v.28 z v.28 rs-449/v.36 1 0 1 1 1 v.11 v.11 v.11 z v.11 v.11 z v.10 z v.10 v.28/rs-232 1 1 0 1 1 v.28 v.28 v.28 z v.28 v.28 z v.28 z v.28 no cable 1 1 1 1 1 z z z z z z z z z z table 2. max13173e mode selection
max13171e/max13173e/MAX13175E multiprotocol, pin-selectable data interface chipset ______________________________________________________________________________________ 25 as shown in figure 16, in v.11 mode, switch s1 is closed and switch s2 is open, presenting 104 ? across terminals a and b. in v.35 mode, switches s1 and s2 are both closed, presenting a t-network with 104 ? dif- ferential impedance and 153 ? common-mode imped- ance. in high-impedance mode, switches s1 and s2 are both open, presenting a high impedance across terminals a and b suitable for v.28 and v.10 modes. the state of the MAX13175E? mode-select inputs, m0, m1, m2, and dce/ dte determines the mode of each of the six termination networks. table 3 shows a cross-ref- erence of termination mode and select input state for each of the six termination networks within the MAX13175E. r2 52 ? r3 127 ? r1 52 ? s1 closed a b s2 open (a) v.11 (b) v.35 (c) z a c b a b MAX13175E r2 52 ? r3 127 ? r1 52 ? s1 closed s2 closed r2 52 ? r3 127 ? r1 52 ? s1 open s2 open cc MAX13175E MAX13175E figure 16. termination modes protocol dce/ dte m2 m1 m0 r1 r2 r3 r4 r5 r6 v.10/rs-423 0 0 0 0 z z z z z z rs-530a 0 0 0 1 z z z v.11 v.11 v.11 rs-530 0 0 1 0 z z z v.11 v.11 v.11 x.21 0 0 1 1 z z z v.11 v.11 v.11 v.35 0 1 0 0 v.35 v.35 z v.35 v.35 v.35 rs-449/v.36 0 1 0 1 z z z v.11 v.11 v.11 v.28/rs-232 0 1 1 0 z z z z z z no cable 0 1 1 1 v.11 v.11 v.11 v.11 v.11 v.11 v.10/rs-423 1 0 0 0 z z z z z z rs-530a 1 0 0 1 z z z z v.11 v.11 rs-530 1 0 1 0 z z z z v.11 v.11 x.21 1 0 1 1 z z z z v.11 v.11 v.35 1 1 0 0 v.35 v.35 v.35 z v.35 v.35 rs-449/v.36 1 1 0 1 z z z z v.11 v.11 v.28/rs-232 1 1 1 0 z z z z z z no cable 1 1 1 1 v.11 v.11 v.11 v.11 v.11 v.11 table 3. MAX13175E termination mode selection
max13171e/max13173e/MAX13175E multiprotocol, pin-selectable data interface chipset 26 ______________________________________________________________________________________ no-cable mode the max13171e/max13173e enter no-cable mode when the mode-select inputs are left unconnected or connected high (m0 = m1 = m2 = 1). the receiver out- puts enter a high-impedance state in no-cable mode, allowing these output lines to be shared with other receiver outputs (the receiver outputs have an internal pullup resistor to pull the outputs high if not driven). also, in no-cable mode, the transmitter outputs enter a high-impedance state, so these output lines can be shared with other devices. the MAX13175E enters no-cable mode when the mode select inputs, m0, m1, and m2 are connected high. in no-cable mode, all six termination networks are placed in v.11 mode, with s1 closed and s2 open. v l logic supply the max13171e/max13173e/MAX13175E include a v l logic supply that allows user-defined interface logic- voltage levels referenced to v l . v l can go down to +1.62v and up to v cc . all logic inputs and outputs are referred to v l . data rate the max13171e/max13173e/MAX13175E support a maximum data rate of 40mbps in rs-449/v.36, rs-530, rs-530a, x.21, v.35 if only one of the max13171e high-speed transceivers is operated at the maximum data rate. if two high-speed transceivers operate simul- taneously, the maximum data rate is 20mbps. applications information capacitor selection the capacitors used for the charge pumps, as well as for supply bypassing, must have a low equivalent series resistance (esr), low inductance (esl), and low temperature coefficient. multilayer ceramic capacitors with an x7r dielectric offer the best combination of per- formance, size, and cost. the flying capacitors (c1, c2) should have a value of 1?, while the bypass capacitor (c4) and reservoir capacitors (c3, c5) should have a minimum value of 4.7? (figure 15). to reduce the rip- ple present on the transmitter outputs, capacitors c3, c4, and c5 can be increased. the values of c1 and c2 should not be increased. cable mode-select application a cable-selectable multiprotocol interface is shown in figure 17. the mode control lines m0, m1, and dce/ dte are wired to the db-25 connector. to select the serial interface mode, the appropriate combination of m0, m1, and dce/ dte are grounded within the cable wiring. the control lines that are not grounded are pulled high by the internal pullups on the max13171e/max13173e. the serial interface protocol of the max13171e/ max13173e/MAX13175E is selected based on the cable that is connected to the db-25 interface. v.10 (rs-423) interface (max13173e only) the v.10 interface (figure 18) is an unbalanced single- ended interface capable of driving a 450 ? load. the v.10 driver generates a minimum v o voltage of ?v across a?and c?when unloaded, and a minimum volt- age of 0.9 x v o when loaded with 450 ? . the v.10 receiver has a single-ended input and does not reject common-mode differences between c and c? the v.10 receiver-input trip threshold is defined between +50mv and +250mv with input impedance characteristic shown in figure 19. the max13173e v.10 mode receiver has a threshold between +50mv and +250mv. to ensure that the receiver has proper fail-safe operation, see the fail- safe section. to aid in rejecting system noise, the max13173e v.10 receiver has a typical hysteresis of 25mv. switch s3 in figures 20a and 20b is open in v.10 mode to disable the v.28 5k ? termination at the receiver input. switch s4 is closed and switch s5 is open to internally ground the receiver b input.
max13171e/max13173e/MAX13175E multiprotocol, pin-selectable data interface chipset ______________________________________________________________________________________ 27 cts a 4 25 21 18 2 14 24 11 15 12 17 9 3 16 7 19 20 23 8 10 6 22 5 13 cts b dsr a dsr b dcd a dcd b dtr a dtr b rts a rts b rxd a rxd b rxc a rxc b txc a txc b scte a scte b txd a txd b charge pump dte dce rts a rts b dtr a dtr b dcd a dcd b dsr a dsr b cts a cts b txd a txd b scte a scte b txc a txc b rxc a rxc b rxd a rxd b sg charge pump m2 0.1 f 0.1 f c5 4.7 f c2 1 f c4 4.7 f v ee v dd t1 t2 t3 r1 r2 r3 t1outa t1outb t2outa t2outb t3outa/r1ina t3outb/r1inb r2ina r2inb r3ina r3inb v cc t1in t2in t3in r1out r2out r3out v cc r1a r1b r2a r2b r3a r3b r4a r4b r5a r5b r6a r6b 100pf 100pf 100pf m1 m0 dce/dte m1 m2 dce/dte m0 v l latch MAX13175E max13171e t1 t2 t3 t4 r1 r2 r3 t1outa t1outb v ee v ee v dd v cc c1 1 f c4 4.7 f t2outa t2outb t3outa/r1ina t3outb/r1inb r2ina r2inb r3ina r3inb 0.1 f r4 nc v l nc m1 m2 dce/dte invert m0 db-25 connector max13173e 0.1 f 1 shield dte_txd/dce_rxd dte_scte/dce_rxc dte_txc/dce_txc dte_rxc/dce_scte dte_rxd/dce_txd dte_rts/dce_cts dte_dtr/dce_dsr dte_dcd/dce_dcd dte_dsr/dce_dtr dte_cts/dce_rts r1out t2in t3in t1in r2out r3out m1 dce/dte m0 t5outa/r5ina t4outa/r4ina r5 t5 t4in r4out r5out/t5in c5 4.7 f c3 4.7 f c2 1 f v dd c1 1 f c3 4.7 f 0.1 f v l 0.1 f v l figure 17. cable-selectable multiprotocol dce/dte port with db-25 connector
max13171e/max13173e/MAX13175E multiprotocol, pin-selectable data interface chipset 28 ______________________________________________________________________________________ a c generator unbalanced interconnecting cable cable termination receiver load a c figure 18. typical v.10/v.28 interface -3.25ma +3.25ma -10v +10v -3v +3v v z i z figure 19. receiver input impedance curve r6 11k ? r8 5k ? a b c a b gnd r5 55k ? 1.4v r7 11k ? r4 55k ? max13171e max13173e s3 receiver s2 s1 + - figure 20a. v.10 internal resistance network for receivers 1, 2, and 3 r6 11k ? r8 5k ? a c a gnd r5 55k ? max13173e s3 receiver figure 20b. v.10 internal resistance network for receivers 4 and 5
max13171e/max13173e/MAX13175E multiprotocol, pin-selectable data interface chipset ______________________________________________________________________________________ 29 v.11 (rs-422) interface as shown in figure 21, the v.11 protocol is a fully bal- anced differential interface. the v.11 driver generates a minimum of ?v between nodes a and b when a 100 ? (min) resistance is present at the load. the v.11 receiver is sensitive to differential signals of ?00mv at receiver inputs a?and b? the v.11 receiver input must comply with the impedance curve of figure 22 and reject com- mon-mode signals developed across the cable (refer- enced from c to c?in figure 21) of up to ?v. the max13171e/max13173e v.11 mode receivers have a differential threshold between -50mv and -200mv to ensure that the receiver has fail-safe opera- tion (see the fail-safe section.) to aid in rejecting sys- tem noise, the max13171e/max13173e v.11 receivers have a typical hysteresis of 15mv. switch s3 in figure 23 is open in v.11 mode to disable the v.28 5k ? termi- nation at the inverting receiver input. because the con- trol signals are slow (60kbps), 100 ? termination resistance is generally not required for the max13173e. for high-speed data transmission, the v.11 specifica- tion recommends terminating the cable at the receiver with a 100 ? resistor. this resistor, although not required, prevents reflections from corrupting transmit- ted data. in figure 23, the MAX13175E is used to termi- nate the v.11 receiver. internal to the MAX13175E, s1 is closed and s2 is open to present a 100 ? minimum dif- ferential resistance. the max13171e? internal v.28 ter- mination is disabled by opening s3. r6 11k ? r8 5k ? r3 127 ? r2 52 ? r1 52 ? a b c a b gnd r5 55k ? 1.4v r7 11k ? r4 55k ? MAX13175E max13171e s3 s1 receiver s2 s2 + - s1 figure 23. v.11 termination and internal resistance networks 100 ? min a b c a b c generator balanced interconnecting cable cable termination receiver load figure 21. typical v.11 interface -3.25ma +3.25ma -10v +10v -3v +3v v z i z figure 22. receiver input impedance
max13171e/max13173e/MAX13175E multiprotocol, pin-selectable data interface chipset 30 ______________________________________________________________________________________ v.28 (rs-232) interface the v.28 interface is an unbalanced single-ended inter- face (figure 18). the v.28 driver generates a minimum of ?v across the 3k ? load impedance between a?and c? the v.28 receiver has a single-ended input. the max13171e/max13173e v.28 mode receivers have a threshold between +0.8v and +2.0v. to aid in reject- ing system noise, the max13171e/max13173e v.28 receivers have a typical hysteresis of 250mv. switch s3 in figures 24a and 24b is closed in v.28 mode to enable the 5k ? v.28 termination at the receiver inputs. v.35 interface figure 25 shows a fully-balanced, differential standard v.35 interface. the generator and the load must both present a 100 ? ?0 ? differential impedance and a 150 ? ?5 ? common-mode impedance as shown by the resistive t-networks in figure 26. the v.35 driver generates a current output (?1ma, typ) that develops an output voltage of ?50mv across the generator and load termination networks. the v.35 receiver is sensi- tive to ?00mv differential signals at receiver inputs a and b? the v.35 receiver rejects common-mode sig- nals developed across the cable (referenced from c to c? of up to ?v, allowing for error-free reception in noisy environments. in figure 26, the MAX13175E is used to implement the resistive t-network that is needed to properly terminate the v.35 driver and receiver. internal to the MAX13175E, s1 and s2 are closed to connect the t- network resistors to the circuit. the v.28 termination resistor (internal to the max13171e) is disabled by opening s3 to avoid interference with the t-network impedance. the v.35 specification allows for ?v of ground differ- ence between the v.35 generator and v.35 load. the max13174e maintains correct termination impedance over this condition. r6 11k ? r8 5k ? a b c a b gnd r5 55k ? 1.4v r7 11k ? r4 55k ? max13171e max13173e s3 receiver s2 s1 + - figure 24a. v.28 termination and internal resistance network for receiver 1, 2, and 3 r6 11k ? r8 5k ? a c a gnd r5 55k ? max13173e s3 receiver figure 24b. v.28 internal resistance network for receiver 4 and 5
max13171e/max13173e/MAX13175E multiprotocol, pin-selectable data interface chipset ______________________________________________________________________________________ 31 dte/dce mode applications the max13171e/max13173e can be hardwired for either dte or dce mode in one of two ways: a dedicat- ed dte or dce port with an appropriate gender con- nector, or a port with a connector that can be configured for dte or dce operation by rerouting the signals to the max13171e and max13173e, using a dedicated dte cable or dedicated dce cable. the interface mode is selected by logic outputs from the controller or from jumpers to either v l or gnd on the mode select inputs. a dedicated dce port using a db-25 female connector is shown in figure 28. figure 29 illustrates a dedicated dte port using a db-25 male connector. figure 27 shows an application circuit with one com- mon db-25 connector that can be configured for either dte or dce mode. the configuration requires separate cables for proper signal routing in dte or dce opera- tion. figure 27 illustrates a dce or dte controller-selec- table interface. the dce/ dte and invert inputs switch the port? mode of operation (tables 1, 2). 50 ? 50 ? 125 ? 50 ? 50 ? 125 ? a b c a b c gnd gnd generator balanced interconnecting cable cable termination receiver load figure 25. typical v.35 interface r6 11k ? r8 5k ? r3 127 ? r2 52 ? r1 52 ? a b c a b gnd r5 55k ? 1.4v r7 11k ? r4 55k ? MAX13175E max13171e s3 s1 receiver s2 s1 + - s2 figure 26. v.35 termination and internal resistance networks
max13171e/max13173e/MAX13175E multiprotocol, pin-selectable data interface chipset 32 ______________________________________________________________________________________ cts a 4 2 14 24 11 15 12 17 9 3 16 7 19 20 23 8 10 6 22 5 13 cts b dsr a dsr b dcd a dcd b dtr a dtr b rts a rts b rxd a rxd b rxc a rxc b txc a txc b scte a scte b txd a txd b charge pump dte dce rts a rts b dtr a dtr b dcd a dcd b dsr a dsr b cts a cts b txd a txd b scte a scte b txc a txc b rxc a rxc b rxd a rxd b sg charge pump m2 0.1 f 0.1 f c5 4.7 f c2 1 f c4 4.7 f v ee v dd t1 t2 t3 r1 r2 r3 t1outa t1outb t2outa t2outb t3outa/r1ina t3outb/r1inb r2ina r2inb r3ina r3inb v cc t1in t2in t3in r1out r2out r3out v cc r1a r1b r2a r2b r3a r3b r4a r4b r5a r5b r6a r6b 100pf 100pf 100pf m1 m0 dce/dte m1 m2 dce/dte m0 latch MAX13175E max13171e t1 t2 t3 t4 r1 r2 r3 t1outa t1outb v ee v ee v dd v cc c1 1 f c4 4.7 f t2outa t2outb t3outa/r1ina t3outb/r1inb r2ina r2inb r3ina r3inb 0.1 f r4 v l m1 m2 dce/dte invert m0 db-25 connector max13173e 0.1 f 1 shield dte_txd/dce_rxd dte_scte/dce_rxc dte_txc/dce_txc dte_rxc/dce_scte dte_rxd/dce_txd dte_rts/dce_cts dte_dtr/dce_dsr dte_dcd/dce_dcd dte_dsr/dce_dtr dte_cts/dce_rts dte_ll/dce_ll r1out t2in t3in t1in r2out r3out t5outa/r5ina t4outa/r4ina r5 t5 t4in r4out r5out/t5in c5 4.7 f c3 4.7 f c2 1 f v dd c1 1 f c3 4.7 f 0.1 f v l 0.1 f v l dce/dte m2 m1 m0 invert figure 27. controller-selectable multiprotocol dce/dte port with db-25 connector
max13171e/max13173e/MAX13175E multiprotocol, pin-selectable data interface chipset ______________________________________________________________________________________ 33 4 3 16 17 9 15 12 24 11 2 14 7 19 20 23 8 10 20 23 4 19 18 charge pump dce cts a cts b dsr a dsr b dcd a (109) dcd b dtr a (108) dtr b rts a (105) rts b ll a (141) rxd a (104) rxd b rxc a (115) rxc b txc a (114) txc b scte a (113) scte b txd a (103) txd b sg charge pump m2 0.1 f 0.1 f c5 4.7 f c2 1 f c4 4.7 f v ee v dd t1 t2 t3 r1 r2 r3 t1outa t1outb t2outa t2outb t3outa/r1ina t3outb/r1inb r2ina r2inb r3ina r3inb v cc t1in t2in t3in r1out r2out r3out v cc r1a r1b r2a r2b r3a r3b r4a r4b r5a r5b r6a r6b 100pf 100pf 100pf m1 m0 dce/dte m1 m2 dce/dte m0 latch MAX13175E max13171e t1 t2 t3 t4 r1 r2 r3 t1outa t1outb v ee v ee v dd v cc c1 1 f c4 4.7 f t2outa t2outb t3outa/r1ina t3outb/r1inb r2ina r2inb r3ina r3inb 0.1 f r4 v l m1 m2 dce/dte invert m0 db-25 female connector max13173e 0.1 f 1 shield (101) rxd rxc txc scte txd cts dsr dcd dtr rts ll r1out t2in t3in t1in r2out r3out t5outa/r5ina t4outa/r4ina r5 t5 t4in r4out r5out/t5in c5 4.7 f c3 4.7 f c2 1 f v dd c1 1 f c3 4.7 f 0.1 f v l 0.1 f v l m2 m1 m0 invert v l nc nc figure 28. controller-selectable dce port with db-25 connector
max13171e/max13173e/MAX13175E multiprotocol, pin-selectable data interface chipset 34 ______________________________________________________________________________________ 4 2 14 24 11 15 12 17 9 3 14 7 19 20 23 8 10 6 22 5 13 18 charge pump dte rts a (105) rts b dtr a (108) dtr b dcd a (109) dcd b dsr a (107) dsr b cts a (106) cts b ll a (141) txd a (103) txd b scte a (113) scte b txc a (114) txc b rxc a (115) rxc b rxd a (104) rxd b sg charge pump m2 0.1 f 0.1 f c5 4.7 f c2 1 f c4 4.7 f v ee v dd t1 t2 t3 r1 r2 r3 t1outa t1outb t2outa t2outb t3outa/r1ina t3outb/r1inb r2ina r2inb r3ina r3inb v cc t1in t2in t3in r1out r2out r3out v cc r1a r1b r2a r2b r3a r3b r4a r4b r5a r5b r6a r6b 100pf 100pf 100pf m1 m0 dce/dte m1 m2 dce/dte m0 latch MAX13175E max13171e t1 t2 t3 t4 r1 r2 r3 t1outa t1outb v ee v ee v dd v cc c1 1 f c4 4.7 f t2outa t2outb t3outa/r1ina t3outb/r1inb r2ina r2inb r3ina r3inb 0.1 f r4 v l m1 m2 dce/dte invert m0 db-25 male connector max13173e 0.1 f 1 shield (101) txd scte txc rxc rxd rts dtr dcd dsr cts ll r1out t2in t3in t1in r2out r3out t5outa/r5ina t4outa/r4ina r5 t5 t4in r4out r5out/t5in c5 4.7 f c3 4.7 f c2 1 f v dd c1 1 f c3 4.7 f 0.1 f v l 0.1 f v l m2 m1 m0 invert figure 29. controller-selectable multiprotocol dte port with db-25 connector
max13171e/max13173e/MAX13175E multiprotocol, pin-selectable data interface chipset ______________________________________________________________________________________ 35 t1 t2 t3 r3 r2 r1 t1 t2 t3 d4 txd scte txc rxc rxd ll t4 r4 t4 r3 r2 r1 104 ? 104 ? 104 ? 104 ? 104 ? max13171e MAX13175E MAX13175E max13171e t1 t2 t3 r3 r2 r1 t3 t2 t1 rts dtr dcd dsr cts r1 r2 r3 max13173e max13173e serial controller txd scte txc rxc rxd rts dtr dcd dsr cts ll serial controller txd scte txc rxc rxd rts dtr dcd dsr cts ll dce dte figure 30. dce-to-dte x.21 interface complete multiprotocol x.21 interface a complete dte-to-dce interface operating in x.21 mode is shown in figure 30. the max13171e is used to generate the clock and data signals, and the max13173e generates the control signals and local loopback (ll). the MAX13175E is used to terminate the clock and data signals to support the v.11 protocol for cable termination. the control signals do not need external termination. esd protection esd-protection structures are incorporated on all pins to protect against electrostatic discharges encountered during handling and assembly. the driver outputs and receiver inputs of the max13171e/max13173e have extra protection against static electricity. maxim? engi- neers have developed state-of-the-art structures to pro- tect these pins against esd of ?5kv without damage. the esd structures withstand high esd in all states: nor- mal operation, shutdown, and powered down. after an esd event, the max13171e/max13173e/MAX13175E keep working without latchup or damage. esd protec- tion can be tested in various ways. the electrical characteristics table shows the various limits for each device and they are characterized for protection to the following methods: human body model contact method specified in iec 61000-4-2 air-gap discharge method specified in iec 61000-4-2
max13171e/max13173e/MAX13175E multiprotocol, pin-selectable data interface chipset 36 ______________________________________________________________________________________ esd test conditions esd performance depends on a variety of conditions. contact maxim for a reliability report that documents test setup, test methodology, and test results. human body model figure 31a shows the human body model, and figure 31b shows the current waveform it generates when dis- charged into a low impedance. this model consists of a 100pf capacitor charged to the esd voltage of interest, which is then discharged into the test device through a 1.5k ? resistor. iec 61000-4-2 the iec 61000-4-2 standard covers esd testing and performance of finished equipment. however, it does not specifically refer to integrated circuits. the max13171e/max13173e/MAX13175E help equipment designs to meet iec 61000-4-2, without the need for additional esd-protection components. the major difference between tests done using the human body model and iec 61000-4-2 is higher peak current in iec 61000-4-2 because series resistance is lower in the iec 61000-4-2 model. figure 31c shows the iec 61000-4-2 model, and figure 31d shows the current waveform for the iec 61000-4-2 esd contact discharge test. charge-current limit resistor discharge resistance storage capacitor c s 100pf r c 1m ? r d 1500 ? high- voltage dc source device under test figure 31a. human body esd test model charge-current limit resistor discharge resistance storage capacitor c s 150pf r c 50m ? to 100m ? r d 330 ? high- voltage dc source device under test figure 31b. human body current waveform i p 100% 90% 36.8% t rl time t dl current waveform peak-to-peak ringing (not drawn to scale) i r 10% 0 0 amps figure 31c. ice 61000-4-2 esd test model t r = 0.7ns to 1ns 30ns 60ns t 100% 90% 10% i peak i figure 31d. iec 61000-4-2 esd generator current waveform
max13171e/max13173e/MAX13175E multiprotocol, pin-selectable data interface chipset ______________________________________________________________________________________ 37 pin configurations max13171e 31 30 29 28 27 26 25 24 23 22 21 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 38 37 36 35 34 33 32 m1 m2 dce/dte v cc r3inb r3ina gnd v dd c1+ c1- gnd c2+ c2- v ee t3in n.c. t2in t1in v cc n.c. n.c. v l m0 r3out r2out r1out t2outb t2outa t1outb t1outa gnd n.c. n.c. r2inb r2ina t3outb/r1inb t3outa/r1ina gnd tqfn *connect exposed pad to v ee . + *ep max13173e 31 30 29 28 27 26 25 24 23 22 21 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 38 37 36 35 34 33 32 m1 m2 dce/dte invert t4outa/r4ina gnd r3inb v dd c1+ c1- gnd c2+ c2- v ee r2out r1out v l t3in t2in v cc t1in m0 r4out t4in r5out/t5in r3out gnd t2outb t2outa t1outb t1outa t5outa/r5ina gnd r3ina r2inb r2ina t3outb/r1inb t3outa/r1ina tqfn *connect exposed pad to v ee . + *ep top view
max13171e/max13173e/MAX13175E multiprotocol, pin-selectable data interface chipset maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 38 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2009 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . package type package code document no. 38 tqfn-ep t3857-1 21-0172 pin configurations (continued) MAX13175E 31 30 29 28 27 26 25 24 23 22 21 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 38 37 36 35 34 33 32 gnd r3c v l v ee v dd gnd v cc r1b r1c m0 m1 m2 latch dce/dte r2b r2b r2a r2a r1a r1a r1b r3b r3b r3a r3a r2c r5b r5a r5a r6a r6a r6b r6b r4b r4b r4a r4a r5b tqfn *connect exposed pad to v ee + *ep top view chip information process: bicmos

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